XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 28

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
C7
D9
TXPOHCLK
TXPOH
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
O
I
TTL
TTL
Transmit Path Overhead Input Port – Input pin.
This pin is used for the Transmit AU-4/VC-4 Mapper POH
Processor Block when TUG-3 mapping is used.
This input pin permits the user to insert the POH data into the
Transmit AU-4/VC-4 Mapper POH Processor blocks for
insertion and transmission via the “outbound” STS-3 signal.
In this mode, the external circuitry (which is being interfaced to
the “Transmit Path Overhead Input Port” is suppose to monitor
the following output pins;
• TxPOHFrame_n
• TxPOHEnable_n
• TxPOHClk_n
The “TxPOHFrame_n” output pin will toggle “high” upon the
rising
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within J1 byte (e.g., the first
POH byte).
“high” for eight consecutive “TxPOHClk_n” periods.
external circuitry should use this pin to note STS-1 SPE frame
boundaries.
The “TxPOHEnable_n” output pin will toggle “high” upon the
rising
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within a given POH byte. To
externally insert a given POH byte:
This data bit will be sampled upon the very next falling edge of
“TxPOHClk_n”. The external circuitry should continue to keep
the “TxPOHIns_n” input pin “high” and advancing the next bits
(within
“TxPOHClk_n”.
Transmit Path Overhead Input Port – Clock Output pin:
This pin is used for the Transmit AU-4/VC-4 Mapper POH
Processor Block when TUG-3 mapping is used.
This output pin, along with “TxPOH”, “TxPOHEnable”,
“TxPOHIns” and “TxPOHFrame” function as the “Transmit
Path Overhead (TxPOH) Input Port”.
The “TxPOHFrame” and “TxPOHEnable” output pins are
updated upon the falling edge this clock output signal. The
“TxPOHIns” input pins and the data residing on the “TxPOH”
input pins are sampled upon the next falling edge of this clock
signal.
28
(1) assert the “TxPOHIns_n” input pin by toggling it
(2) place the value of the first bit (within this particular
edge
edge
the
“high”, and
POH byte) on this input pin upon the very next rising
edge of “TxPOHClk_n”.
POH
The “TxPOHFrame_n” output pin will remain
of
of
bytes)
“TxPOHClk_n”
“TxPOHClk_n”
upon
each
approximately
approximately
xr
rising
edge
one
The
one
of