XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 246

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
This step configures the Transmit STS-3c POH Processor block to use the “TxPOH_n” input port as the
source for the Z3 byte, within each “outbound” STS-3c SPE. In this mode, the Transmit STS-3c POH
Processor block will accept the value, corresponding to the Z3 byte (via the “TxPOH_n” input port) and it will
write this data into the Z3 byte position, within the “outbound” STS-3c SPE.
STEP 2 – Begin providing the values of the “outbound” Z3 byte to the “TxPOH_n” input port.
The procedure for applying the Z3 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the Z3 byte value into the outbound STS-3c SPE data-stream
If the user intends to externally insert the Z3 byte into the outbound STS-3c SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 42.
Figure 42: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 48 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
the most significant bit) of the “outbound” Z3 byte onto the “TxPOH_n” input pin, upon the very next falling
edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
The “TxPOHIns_n” line (in Figure 42) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the Z3 byte is the seventh byte within the POH.
executed “STEP 1” above.
XRT95L34 Device
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
246
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
xr