XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 169

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XRT94L33IB-L

Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheets

Specifications of XRT94L33IB-L

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
XRT94L33 can be thought of as consisting of four ATM UNIs within a single package (one for each STS-3c
port within the device).
It is important to note that although the XRT94L33 consists of a single “Transmit UTOPIA Interface” block, the
XRT94L33 can be assigned four unique (4) Transmit UTOPIA Addresses as presented in Section
4.2.1.2.1.4.2.1.
2.2.1.3.11
After the ATM Layer processor has “polled” each of the UNI devices, within its system, it must now select a
UNI, and begin writing ATM cell data to that device. The ATM Layer processor makes its selection and
begins the writing process by:
Negate the TxUEnB* signal. This step causes the “addressed” UNI to recognize that it has been selected to
Assert the TxUEnB* signal.
Assert the TxUSoC input pin.
Begin applying the ATM Cell data in a byte-wide (or word-wide) manner to the Transmit UTOPIA Data Bus
At this point, ATM cell data is now being written into the TxFIFO associated with the newly selected UNI.
Figure 17 presents a flow-chart that depicts the “UNI Device Selection and Write” process in Multi-PHY
operation.
Figure 17: Flow-Chart of the “UNI Device Selection and Write Procedure” for the Multi-PHY Operation
Figure 18 presents a timing diagram that illustrates the behavior of various “Transmit UTOPIA Interface block”
signals; during the “Multi-PHY” UNI Device Selection and Write operation.
receive the next set of ATM cell data from the ATM Layer processor.
(TxUData[15:0]).
1. Applying the UTOPIA Address of the “target” UNI on the “Transmit UTOPIA Address Bus”
(TxUAddr[4:0]).
Writing ATM Cell Data into a Different UNI
Begin writing ATM cell data into “Selected” UNI
1. Assert TxUEnB*
2. Place first byte/word of ATM cell onto the “Transmit
UTOPIA Data Bus & Assert TxUSoC
Select “Available” UNI
1. Apply UTOPIA Address of the Transmit UTOPIA
Interface block onto the “UTOPIA Address” bus.
2. Negate the TxUEnB* signal
Poll all UNIs within the “Multi-PHY” System.
Determine which UNIs are “Available”
Continue to write ATM Cell data
Check the TxUClav level after
writing 48 bytes of cell data.
START
169
No
ATM cell data to be
written to selected
there any more
UNI?
Is
Yes
Yes
TxUClav
“High”
Is
?
Wait for TxUClav to toggle “high”
Yes
Continue to poll UNI and
TxUClav
“High”
No
Is
?
No
XRT94L33
Rev.1.2.0.

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