XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 223

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
By writing this particular value into these bit-fields the user is specifying the value that the “Transmit STS-3c
POH Processor” block will set the RDI-P bit-fields (within the G1 byte of the outbound STS-3c frame) to
whenever the corresponding Receive STS-3c POH Processor block declares the TIM-P condition.
STEP 2 – Set Bit 4 (Transmit RDI-P upon TIM-P) within the “Transmit STS-3c Path – RDI-P Control
Register – Byte 1”; to “1” as illustrated below.
Transmit STS-3c Path – RDI-P Control Register – Byte 1 (Address = 0x19CA)
This step configures the Transmit STS-3c POH Processor block to transmit the RDI-P indicator (per the
values written into Bits 3 through 1, within this register); anytime the corresponding “Receive STS-3c POH
Processor” block declares the “TIM-P” condition.
2.2.7.3.2.7
The user can configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P
indicator, in response to the corresponding Receive STS-3c POH Processor block declaring the LCD-P
condition, by executing the following steps.
STEP 1- Write the appropriate value into Bit 7 through 5 (LCD-P RDI-P Code[2:0]) within the “Transmit
STS-3c Path – RDI-P Control Register – Byte 2” as illustrated below.
Transmit STS-3c Path – RDI-P Control Register – Byte 2 (Address = 0x19C9)
By writing this particular value into these three bit-fields, the user is specifying the values that the “Transmit
STS-3c POH Processor” block will set the RDI-P bit-fields (within the outbound G1 byte) to, whenever the
corresponding Receive STS-3c POH Processor block declares the LCD-P condition.
B
B
R/W
R/W
IT
IT
X
X
7
7
LCD-P RDI-P Code[2:0]
TIM-P RDI-P Code[2:0]
Configuring the Transmit STS-3c POH Processor block to automatically transmit RDI-
P, in response to declaration of the LCD-P Condition
B
B
R/W
R/W
IT
X
IT
X
6
6
B
B
R/W
R/W
IT
IT
X
X
5
5
RDI-P upon
RDI-P upon
Transmit
Transmit
LCD-P
TIM-P
B
B
R/W
R/W
IT
IT
1
0
4
4
223
B
B
R/W
R/W
IT
IT
X
X
3
3
UNEQ-P RDI-P Code[2:0]
PLM-P RDI-P Code[2:0]
B
B
R/W
R/W
IT
IT
X
X
2
2
B
B
R/W
R/W
IT
IT
X
X
1
1
XRT94L33
RDI-P upon
RDI-P upon
Transmit
UNEQ-P
Transmit
PLM-P
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
X
0
0
0