XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 382

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
SF CLEARANCE CRITERIA –
In this case, the user specifies two parameters to define the SF Clearance criteria.
• The maximum number of B2 errors (e.g., a B2 error-threshold) accumulated over a given “SF Clear
Interval” time period.
• The length (in terms of SONET frame periods) of this “SF Clear Interval” time period.
Once the user defines these parameters, then the Receive STS-3 TOH Processor block will begin to count
the cumulative number of B2 errors that it detects within a “sliding window” of time. The length of this “sliding
window of time” is dictated by the user-defined “SF Clear Interval” time period.
If the Receive STS-3 TOH Processor block is currently declaring the SF condition, and if it continues to detect
more than the “B2 error threshold” number of B2 errors; within the “SF Clear Interval” of time, then it will NOT
clear the SF condition. Conversely, if the Receive STS-3 TOH Processor block detects less than the “B2
error threshold” number of B2 errors, within the “SF Clear Interval” of time, then it will clear the SF condition.
S
The user can specify the “B2 Error Threshold” by writing the appropriate value into the “Receive STS-3
Transport – Receive SF Burst Error Tolerance – Byte 1 and Byte 0” registers, as depicted below.
Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address = 0x1156)
Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address = 0x1157)
Notes:
The “Receive STS-3 Transport- Receive SF Burst Error Tolerance – Byte 1 and Byte 0” registers permit the user to write
The “default” value for the “B2 Error Threshold” is “0xFFFF”.
The “Receive STS-3 Transport – Receive SF Burst Error Tolerance” registers are used to set both the “SF Declaration”
PECIFYING THE
B
B
R/W
R/W
in a 16-bit expression for the “B2 Error Threshold”.
and “SF Clearance” criteria. Therefore, any value that the user writes into this register (to set the “SF Clearance”
criteria – per the “SF Burst” Detector) will also effect the “SF Declaration” criteria (per the “SF Burst” Detector).
IT
IT
1
1
7
7
“B2 E
B
B
R/W
R/W
IT
IT
1
1
6
6
RROR
T
HRESHOLD
PER THE
B
B
R/W
R/W
IT
IT
1
1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
”
“B
SF_BURST_TOLERANCE[15:8]
SF_BURST_TOLERANCE[7:0]
FOR
URST
C
B
B
R/W
R/W
LEARING
IT
IT
1
1
” SF D
4
4
382
ETECTOR
SF – T
B
B
R/W
R/W
IT
IT
1
1
HE
3
3
SF “B
URST
B
B
R/W
R/W
IT
IT
1
1
” D
2
2
ETECTOR
B
B
R/W
R/W
IT
IT
1
1
1
1
xr
B
B
R/W
R/W
IT
IT
1
1
0
0