XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 433

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive ATM Cell – Memory Control Register (Address = 0xN713)
STEP 6 – Continue to write the contents of the remaining bytes of this ATM cell into the “Cell Insertion
Memory”.
This is accomplished by executing the procedure, outlined in STEP 4, repeatedly for 13 times.
Notes:
As the user writes the contents of an ATM cell into the “Receive Cell Insertion Memory” they must follow the mandated
If the user performs a READ operation to the “Receive ATM Cell – Insertion/Extraction Memory Register – Bytes 3
2.3.4.7
The first four bit-field of each cell header are the GFC bits. The Receive Cell processor will output the
contents of the GFC Nibble-field for each cell that it receives, via the “GFC Nibble Field” serial output port.
The “Receive GFC Nibble-Field” serial output port consists of the following pins.
• RxGFC
• RxGFCClk
• RxGFCMSB
The data is output via the RxGFC output pin. The order of transmission, within a given cell, is with the MSB
first and in descending order until transmitting the LSB bit. Afterwards, the “GFC Nibble-field” serial output
port will output the MSB for the GFC Nibble-field of the next cell. This data is clocked out on the rising edge
of the RxGFCClk output signal. The RxGFCMSB output pin will be pulsed “high” each time the MSB of the
GFC Nibble field, for a given cell, is present at the RxGFC input. Figure 107 presents an illustration depicting
the behavior of the RxGFC Serial Output Port signals.
Figure 107 Illustration of the Behavior of the RxGFC Serial Output Port signals
B
R/O
IT
0
ATM cell byte format, as depicted in Figure 106.
through 0” they will NOT be reading out the contents of the Receive Cell Insertion Buffer. Instead, the user will be
reading out data from the “Receive Cell Extraction” buffer.
7
T
HE
Unused
B
R/O
R
IT
0
ECEIVE
6
GFC N
B
R/O
IT
0
5
IBBLE
-F
Extraction
RESET*
Memory
IELD
B
R/W
IT
1
4
S
ERIAL
Extraction
Memory
O
CLAV
B
R/W
433
UTPUT
IT
0
3
P
ORT
Insertion
Memory
RESET*
B
R/W
IT
1
2
Insertion
Memory
ROOM
B
R/W
IT
1
1
Write SoC
Insertion
Memory
B
R/W
IT
0
0
XRT94L33
Rev.1.2.0.