XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 344

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Once the Receive STS-3 TOH Processor block declares the SEF defect condition, then it will clear the SEF
Defect Condition if it detects 2 consecutive STS-3 frames with un-erred framing alignment (A1 and A2) bytes.
Once the Receive STS-3 TOH Processor block clears the SEF defect condition, then it will alert the
Microprocessor of this fact by doing the following.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.3.6
The Receive STS-3 TOH Processor block is capable of declaring and clearing the LOF (Loss of Frame)
defect condition, as described below.
2.3.1.3.6.1
The Receive STS-3 TOH Processor block will declare the LOF defect anytime the Receive STS-3 TOH
Processor block continuously declares the SEF defect condition for at least 3ms.
Whenever the Receive STS-3 TOH Processor block declares the LOF Defect condition, then it will do the
following.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
RDI-L
RDI-L
B
B
RUR
B
7. It will indicate that it is clearing the SEF defect condition by setting Bit 1 (SEF Defect Declared), within
R/O
8. It will generate the “Change of SEF Defect Condition” Interrupt. The Receive STS-3 TOH Processor
9. It will indicate that it is declaring the LOF defect condition by setting Bit 2 (LOS Defect Declared)
IT
IT
IT
0
0
7
7
7
the Receive STS-3 Transport Status Register – Byte 0” to “0” as depicted below.
block will indicate that it is declaring the “Change of SEF Defect Condition” interrupt by doing the
following.
within the “Receive STS-3 Transport Status Register – Byte 0” to “1” as depicted below.
a. Toggling the “INT*” output pin “LOW”.
b. b. Setting Bit 1 (Change of SEF Defect Condition Interrupt Status), within the Receive STS-3
THE LOF (LOSS OF FRAME) DECLARATION AND CLEARANCE CRITERIA
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
S1 Byte
Transport Interrupt Status Register – Byte 0” to “1”, as illustrated below.
How the Receive STS-3 TOH Processor Block declares the LOF Defect Condition
S1 Byte
Defect
Status
B
B
RUR
B
R/O
IT
IT
IT
0
0
6
6
6
Detection of
K1, K2 Byte
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
B
RUR
B
R/O
IT
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Defect
Status
B
B
Error
B
RUR
R/O
SF
IT
IT
IT
0
0
4
4
4
344
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Defect
Status
B
B
Error
RUR
B
R/O
SD
IT
IT
IT
0
0
3
3
3
LOF Defect
LOF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
B
RUR
LOF
R/O
IT
IT
IT
0
0
2
2
2
SEF Defect
SEF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
B
SEF
R/O
IT
IT
IT
0
1
1
1
1
xr
LOS Defect
LOS Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
B
LOS
R/O
IT
IT
IT
0
0
0
0
0