XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 331

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.2.9.5.14
The Transmit STS-3 TOH Processor block permits the user to either enable or disable scrambling of the STS-
3 data, prior to it being transmitted to the remote terminal equipment. The customer can accomplish this by
writing the appropriate value into Bit 2 (Scramble Enable), within the Transmit STS-3 Transport – SONET
Transmit Control Register, as depicted below.
Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address = 0x1902)
Setting this bit-field to “1” enables the Scrambler.
Scrambler.
If the Scrambler is enabled, then it will scramble the “outbound” STS-3 data with a generating polynomial of x
+ x
2.3
If a given channel (or the entire device) is configured to operate in the ATM Mode, then the purpose of the
Receive Section within the XRT94L33 1-Channel STS-3c/STS-3 ATM UNI device is to permit a local ATM
Layer (or ATM Adaptation Layer) processor to receive ATM cell data from a remote piece of equipment via an
STS-3, STS-3c or DS3/E3 transport medium.
For ATM UNI Applications, the Receive Section of the XRT94L33 chip consists of the following blocks.
• Receive STS-3 TOH Processor Block
• Receive STS-3c POH Processor Block (for STS-3c Applications)
• Receive SONET POH Processor Block (for STS-3 Applications)
• Receive ATM Cell Processor Block
• Receive UTOPIA Interface Block
The Receive STS-3 TOH Processor block will receive an STS-3 signal, either over the PECL interface or via
the Receive STS-3 Telecom Bus Interface. As the Receive STS-3 TOH Processor block receives this signal,
it will do the following.
• It will locate the boundaries of the incoming STS-3 frames
• It will compute and verify the B1 and B2 bytes
• It will detect and clear the LOS, SEF, LOF, RDI-L and AIS-L defect condition
• It will detect and flag REI-L events
• It will detect and clear the SD and SF conditions
• It will route the STS-3c SPE data to the Receive STS-3c POH Processor block for further processing.
The Receive STS-3c POH Processor block will receive the STS-3c SPE data from the Receive STS-3 TOH
Processor block. As the Receive STS-3c POH Processor block receives this signal, it will do the following.
• It will compute and verify the B3 bytes
• It will detect and clear the LOP-P, RDI-P and AIS-P defect conditions
M0M1 Insert
Method[0]
6
B
R/W
+ 1 and a sequence length of 127.
IT
0
7
RECEIVE DIRECTION
SCRAMBLING DATA
Unused
B
R/O
IT
0
6
RDI-L Force
B
R/W
IT
0
5
AIS-L Force
B
R/W
IT
0
4
331
Conversely, setting this bit-field to “0” disables the
LOS Force
B
R/W
IT
0
3
Scramble
Enable
B
R/W
IT
X
2
B2 Error
Insert
B
R/W
IT
0
1
XRT94L33
A1A2 Error
Rev.1.2.0.
Insert
B
R/W
IT
0
0
7