XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 428

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.3.4.6
The Receive ATM Cell Processor block consist of a “Receive Cell Insertion Buffer/Processor” block. Figure
105_ presents the functional block diagram of the Receive ATM Cell Processor block with the Receive Cell
Insertion Buffer/Processor” block highlighted.
Figure 105 Illustration of the Receive ATM Cell Processor block Functional Block Diagram, with the
“Receive Cell Insertion Buffer/Processor” block highlighted
The Receive Cell Insertion Buffer/Processor block permits the user to load the contents of an “outbound” ATM
cell into the “Receive Cell Insertion Buffer” via the Microprocessor Interface. Once this cell has been loaded
into the “Receive Cell Insertion Buffer”, then it will be transmitted to the “RxFIFO” where it will ultimately wait
to be read out of the Receive UTOPIA Interface block via the ATM Layer Processor block. This feature can
be very useful for debugging and diagnostics on the “UTOPIA” side of the chip.
The Format of ATM Cell Data that is written into the “Receive Cell Insertion” Buffer
As the user loads the contents of an ATM cell into the “Receive Cell Insertion” Buffer (via the Microprocessor
Interface), they will be expected to write this ATM cell data into a 32 bit wide register/buffer interface. As a
consequence, the user must write in 56-byte size ATM cells into the “Receive Cell Insertion” buffer.
The byte format of this 56 byte ATM cell is as illustrated below in Figure 106.
Figure 106 Byte-Format of the ATM Cell that is to be loaded into the “Receive Cell Insertion” Memory
Receive UTOPIA
4T
Interface Block
Main Data Path
HE
RxFIFO
RxFIFO
R
ECEIVE
C
ELL
I
NSERTION
Calculation
Calculation
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Parity
Block
Parity
Block
B
UFFER
De-Scrambler
Cell Payload
/P
De-Scrambler
User Cell
Cell Payload
User Cell
Idle Cell
ROCESSOR
Filter
Block
428
Idle Cell
Filter
Block
Filter
Block
Block
Filter
Cell Extraction
Cell Insertion
Cell Extraction
Cell Insertion
Processor
Processor
Verification
Processor
Processor
HEC Byte
Verification
Buffer/
Buffer/
HEC Byte
Buffer/
Buffer/
Block
Block
Receive GFC
Nibble-Field
Receive GFC
Output I/F
Nibble-Field
Output I/F
Microprocessor
Microprocessor
STS-3c/STS-12c
Processor Block
From Receive
Interface
Interface
Block
Block
xr
POH