XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 406

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
1. It will indicate that it has declared the LCD defect condition by setting Bit 0 (LCD Defect Declared) and
Receive ATM Cell Processor Block – Receive ATM Status Register (Address = 0xN707)
2. It will generate the “Declaration of LCD Defect Condition” interrupt. The Receive ATM Cell Processor
Receive ATM Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0 (Address =
0xN70B)
The remaining discussion of the Receive ATM Cell Processor block, within this data sheet, presumes that it
(the Receive ATM Cell Processor block) is operating in the “SYNC” state and properly delineating cells.
Once the Receive ATM Cell Processor is properly delineating cells then it will proceed to route these cells
through a series of “filters”; prior to allowing these cells to be written to the RxFIFO within the Receive
UTOPIA Interface block.
Ultimately, the sequence of filtering/processing that each cell must go through is listed below in sequential
order.
• HEC Byte Verification
• Idle Cell Filtering
• User Cell Filtering
• Cell Payload De-Scrambling
The next few sections discusses each of these forms of “cell filtering”.
Insertion
Interrupt
Receive
Status
B
RUR
B
Cell
Bits 2 and 1 (Cell Delineation Status[1:0]) bit-fields, within the “Receive ATM Cell Processor Block –
Receive ATM Status Register to “1” as depicted below.
R/O
block will indicate that it is declaring the “Declaration of LCD Defect Condition” Interrupt by doing the
following.
IT
IT
0
0
7
7
a. Toggling the “INT*” output pin “low”.
b. Setting Bit 0 (Declaration of LCD Defect Interrupt Status), within the “Receive ATM Cell
Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
Overflow
Interrupt
Receive
Status
FIFO
B
RUR
B
R/O
IT
0
IT
0
6
6
Unused
Extraction
Overflow
Interrupt
Receive
Memory
Status
B
RUR
Cell
B
R/O
IT
0
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Overflow
Insertion
Interrupt
Receive
Memory
Status
B
RUR
Cell
B
IT
0
R/O
IT
0
4
4
406
Detection of
Correctable
HEC Byte
Interrupt
PRBS Lock
Status
B
Error
RUR
Indicator
IT
0
B
R/O
IT
3
0
3
Uncorrectable
Error Interrupt
Detection of
Cell Delineation Status[1:0]
HEC Byte
Status
B
RUR
B
R/O
IT
0
IT
1
2
2
Clearance
Interrupt
of LCD
Defect
Status
B
R/O
B
RUR
IT
1
IT
0
1
xr
1
LCD Defect
Declaration
Declared
Interrupt
of LCD
Defect
Status
B
B
RUR
R/O
IT
IT
1
1
0
0