XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 204

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Transmit ATM Control – Byte 0 (Address = 0xNF03)
In this mode, all ATM cells (even those with HEC byte errors) will pass through the “HEC Byte Calculation &
Insertion” block, without any flagging of HEC byte errors.
Configuring the HEC Byte Calculation & Insertion block to Regenerate (e.g., recompute and insert) the
HEC byte, prior to transmission via the “Transmit Data Path”
In addition to being capable of detecting and flagging HEC byte errors, the “HEC Byte Calculation & Insertion”
block can be configured to recompute and insert a new HEC byte into the fifth octet position within all ATM
cells that are processed by the “HEC Byte Calculation & Insertion” block. The user can implement this
configuration by writing a “1” into Bit 0 (Re-Calculate HEC Byte Enable), within the “Transmit ATM Control –
Byte 1” Register, as depicted below.
Transmit ATM Control – Byte 1 (Address = 0xNF02)
Notes:
Setting this bit-field to “1” configures the “HEC Byte Calculation & Insertion” block to unconditionally compute a new HEC
This bit-field is ignored if Bit 6 (HEC Byte Check Enable) within the “Transmit ATM Control – Byte 0” register (Address =
Other Options available via the “HEC Byte Calculation & Insertion” block
The user has the following additional options via the “HEC Byte Calculation & Insertion” block.
• To modulo-2 add the Coset Polynomial to the HEC byte, prior to transmission.
• To invert the HEC byte
Each of these options is discussed below.
Adding the Coset Polynomial to the HEC Byte
The “HEC Byte Calculation & Insertion” block permits the user to configure it to modulo-2 add the Coset
Polynomal (e.g., x
HEC byte would be written back into the fifth octet position within each outbound ATM cell.
HEC Byte
Test Cell
Enable
Invert
Mode
B
B
R/W
R/W
byte (based upon the value of the first four header bytes of a given ATM cell) and insert this value into the 5
position within each outbound ATM cell.
Calculation & Insertion” block to NOT discard any ATM cells that it receives from upstream circuitry, even those cells
that it determines to contain HEC byte errors.
0xNF03) is set to “0”.
IT
IT
0
0
7
7
Generator –
HEC Byte
One Shot
Test Cell
Enable
Check
B
R/W
B
6
R/W
IT
0
IT
0
+ x
6
6
4
+ x
2
Parity Check
+ 1) to the CRC-8 value (e.g., the HEC byte). Afterwards, this “newly computed”
Enable
B
R/W
B
R/W
IT
0
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Discard Cell
upon Parity
B
Error
R/W
B
R/W
Further, this configuration setting also configures the “HEC Byte
IT
X
GFC_Enable[3:0]
IT
0
4
4
204
Odd Parity
B
R/W
B
R/W
IT
X
IT
0
3
3
B
R/O
B
R/W
IT
0
IT
0
2
2
Unused
Addition
B
Coset
R/O
B
R/W
IT
0
IT
0
1
xr
1
Cell Payload
Scramble
HEC Byte
Calculate
Enable
Enable
B
B
R/W
R/W
Re-
IT
X
IT
1
th
0
0
octet