XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 151

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
The Transmit SONET POH Processor or Transmit STS-3c POH Processor block will accept these ATM cells
and will map them into either an STS-1 or STS-3c SPE, respectively. Additionally, the Transmit SONET POH
Processor block or the Transmit STS-3c POH Processor block also has responsibility of generating the POH
bytes for these SPEs, prior to routing this data to the Transmit STS-3 TOH Processor Block.
The Transmit STS-3 TOH Processor Block will take the STS-1 SPE data (from the Transmit SONET POH
Processor block) or the STS-3c SPE (from the Transmit STS-3c POH Processor block) and will generate and
overhead the TOH bytes within each outbound STS-3 frame.
The following sections discuss the blocks comprising the Transmitter Portion of the XRT94L33 in detail.
2.2.1
The Transmit UTOPIA input interface complies with UTOPIA Level 1, 2 and 3 standard interface (e.g., the
Transmit UTOPIA can support both Single-PHY and Multi-PHY operations.) Additionally, the XRT94L33
provides the user with the option of varying the following features associated with the Transmit UTOPIA Bus
Interface.
• Operating the Transmit UTOPIA Data Bus per the UTOPIA Levels 1, 2 or 3 standards
• Transmit UTOPIA Data Bus width of 8 or 16 bits
• The cell size (e.g., the number of octets being processed per cell via the UTOPIA bus)
• Assigning a UTOPIA Address to a given STS-3c port.
• Whether the Transmit UTOPIA Clock De-Skewing PLL is enabled or not.
Figure 10 presents a simplistic illustration of the Transmit UTOPIA Interface block, along with its external
input pins.
Figure 10 A Simple Illustration of the Transmit UTOPIA Interface block
TRANSMIT UTOPIA INTERFACE BLOCK
TFullB*/TxUClav
TFullB*/TxUClav
TxUData[15:0]
TxUData[15:0]
TxUAddr[4:0]
TxUAddr[4:0]
TxUClkO
TxUClkO
TxUEnB*
TxUEnB*
TxUPrty
TxUPrty
TxUSoC
TxUSoC
TxUClk
TxUClk
To Transmit ATM Cell Processor
To Transmit ATM Cell Processor
Transmit UTOPIA
Transmit UTOPIA
151
Interface
Interface
Block
Block
XRT94L33
Rev.1.2.0.