XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 459

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
value of these “Receive UTOPIA Address Bus input pin” signals with that of the contents of its “Rx UTOPIA
Address Register (Address = 0x0513).
If these values do not match, (e.g., RxUAddr[4:0] ≠ 0x03) then UNI #2 will keep its “RxUClav” output signal
“tri-stated”; and will continue to sample its “Receive UTOPIA Address bus input” pins; with each rising edge of
RxUClk.
If these two values do match, (e.g., RxUAddr[4:0] = 0x03) then UNI #2 will drive its “RxUClav” output pin to
the appropriate level, reflecting its RxFIFO “fill-status”. Since the UNI is only operating in the “Cell Level
Handshaking” mode, the UNI will drive the RxUClav output signal “high” if it contains at least one complete
ATM cell of data within its RxFIFO, that needs to be read out by the ATM Layer Processor. Conversely, the
UNI will drive the “RxUClav” output signal “low” if its RxFIFO contains less than one complete ATM cell of
data.
When UNI #2 has been selected for “polling”, UNI #1 will continue to keeps its “RxUClav” output signal “tri-
stated”. Therefore, when UNI #2 is driving its “RxUClav” output pin to the appropriate level; it will be driving
the entire “RxUClav” line, within the “Multi-PHY” system. Consequently, UNI#2 will also be driving the
“RxUClav_in” input pin of the ATM Layer processor (see Figure 117).
If UNI #2 drives the “RxUClav” line “low”, upon the application of its address on the UTOPIA Address Bus,
then the ATM Layer processor will “learn” that there are no ATM cells of data (within the RxFIFO of UNI # 2)
that need to be read out via the “Receive UTOPIA Interface” block. However, if UNI #2 drives the RxUClav
line “high” (during “polling”), then the ATM Layer processor will know that UNI # 2 does contain at least one
ATM cell of data (within its RxFIFO) that needs to be read out via the Receive UTOPIA Interface block.
Figure 118presents a timing diagram, that depicts the behavior of the ATM Layer processor’s and the UNI’s
signals during polling.
Figure 118 Timing Diagram illustrating the Behavior of various signals from the ATM Layer processor
and the UNI, during Polling
Notes regarding Figure 118
The Receive UTOPIA Data bus is configured to be 16 bits wide. Hence, the data, which the ATM Layer processor places
The Receive UTOPIA Interface block is configured to handle 54 bytes/cell. Hence, Figure 92 illustrates the ATM Layer
The ATM Layer processor is currently reading ATM cell data from the Receive UTOPIA Interface block, within UNI #1
The RxFIFO, within UNI#2’s Receive UTOPIA Interface block (RxAddr[4:0] = 0x03) is either depleted or does not contain
The Receive UTOPIA Address of 0x1F is not associated with any UNI device, within this “Multi-PHY” system. Hence, the
on the Receive UTOPIA Data bus, is expressed in terms of 16 bit words: (e.g., W0 - W26).
processor reading 27 words (W0 through W26) for each ATM cell.
(RxAddr[4:0] = 0x01) during this “polling process”.
enough data to constitute a complete ATM cell. Hence, the RxUClav line will be driven “low” whenever this
particular Receive UTOPIA Interface block is “polled”.
RxUClav line is tri-stated whenever this address is “polled”.
RxUAddr[4:0]
RxUData[15:0]
RxUEnB*
RxUClav
RxUSoC
RxUClk
W27
01h
1
1Fh
01h
W0
2
03h
W1
3
03h
1Fh
W2
4
W3
01h
5
459
01h
03h
W4
6
03h
1Fh
W5
7
W6
03h
8
03h
W7
01h
9
01h
1Fh
W8
10
01h
W9
11
01h
W10
03h
12
XRT94L33
Rev.1.2.0.