XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 114

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Figure 1 indicates that the XRT94L33 consists of the following functional blocks.
• The Receive STS-3 PECL Interface Block
• The Receive STS-3 Telecom Bus Interface Block
• The Receive STS-3 TOH Processor Block
• The Receive STS-3c POH Processor Block
• The Receive ATM Cell Processor Block
• The Receive UTOPIA Interface Block
• The Receive PPP Packet Processor Block
• The Receive POS-PHY Interface Block
• The Transmit POS-PHY Interface Block
• The Transmit ATM Cell Processor Block
• The Transmit PPP Packet Processor Block
• The Transmit STS-3c POH Processor Block
• The Transmit STS-3 TOH Processor Block
• The Transmit STS-3 Telecom Bus Interface Block
• The Transmit STS-3 PECL Interface Block
Each of these functional blocks is briefly discussed below. These functional blocks will be discussed in
considerable detail throughout this data sheet.
1.1.1
The purpose of the Clock Synthesizer block is to synthesize a 19.44MHz and a 155.52MHz clock signal from
an externally supplied 19.44MHz reference clock signal.
The Transmit STS-3 TOH and the Transmit STS-3c POH Processor blocks will use these clock signals as its
timing source, for transmitting the outbound STS-3 data either via the PECL interface (e.g., to the optical
transceiver) or via the Telecom Bus Interface, to the remote terminal.
1.1.2
The purpose of the Receive STS-3 PECL Interface and CDR Block is to perform the following functions.
• To receive an STS-3 electrical signal (which is of the PECL format) from either a system back-plane or from
an optical transceiver.
• As the Receive STS-3 PECL Interface block receives this electrical (data) signal, it will route this data-
stream to the “STS-3 Clock and Data Recovery (CDR) Block. This STS-3 CDR block will then generate a
155.52MHz clock and corresponding data signal, which will be routed to the Receive STS-3 TOH Processor
block for further processing.
T
T
HE
HE
C
R
LOCK
ECEIVE
S
YNTHESIZER
STS-3 PECL I
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
B
LOCK
NTERFACE AND
CDR B
114
LOCK
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