XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 444

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
RxUClk - Receive UTOPIA Interface Block - Clock Signal input pin
The Receive UTOPIA Interface block uses this signal to update the data on the Receive UTOPIA Data Bus.
The Receive UTOPIA Interface block also uses this signal to sample and latch the data on the Receive
UTOPIA Address bus pins (during Multi-PHY operation), into the Receive UTOPIA Interface block circuitry.
This clock signal can run at frequencies of up to 50 MHz.
RxUEnB* - Receive UTOPIA Data Bus - Output Enable Input
The Receive UTOPIA Data bus is tri-stated while this input signal is negated. Therefore, the user must assert
this “active-low” signal (toggle it “low”) in order to read the byte (or word) from the Receive UTOPIA Interface
block via the Receive UTOPIA Data bus.
RxUPrty - Receive UTOPIA - Odd Parity Bit output pin
The Receive UTOPIA Interface Block will compute the odd-parity of each byte (or word) of ATM cell data that
it will place on the Receive UTOPIA Data bus. The Receive UTOPIA Data bus will output the value of the
computed parity bit at the RxUPrty output pin, while the corresponding byte (or word) is present on the
Receive UTOPIA Data Bus. This feature allows the ATM Layer Processor to perform parity checking on the
data that it receives from the Receive UTOPIA Interface Block.
RxUSoC - Receive UTOPIA - “Start of Cell” Indicator output pin
The Receive UTOPIA Interface block will pulse this output signal “high”, for one clock period of RxUClk, when
the first byte (or word) of a new cell is present on the Receive UTOPIA Data Bus. This output signal will be
“low” at all other times.
RxUClav/RxEmptyB* - Rx FIFO Cell Available/RxEmpty*
This output signal is used to alert the ATM Layer Processor that the Rx FIFO contains some ATM cell data
that is available for reading. Please see Section 7.4.2.2.1 for more information regarding this signal.
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