XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 342

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.3.1.3.3
Once the Receive STS-3 TOH Processor block reaches this state, it is considered to be operating in a
“Normal” manner. In this mode, the Receive STS-3 TOH Processor block will continue to monitor and check
the value of the Framing Alignment bytes within the incoming STS-3 data-stream.
In general, the Receive STS-3 TOH Processor block will be tolerant to some occasional Framing Byte errors.
However, if the Receive STS-3 TOH Processor block were to detect framing alignment bit errors in four
consecutive SONET frames (within the incoming STS-3 data-stream), then it will declare the “SEF” defect. As
the Receive STS-3 TOH Processor declares the SEF defect, then it will transition into the “SEF = 1, LOF = 0”
state.
As the Receive STS-3 TOH Processor block transitions from the “In-Frame” to the “SEF = 1, LOF = 0” state, it
will do all of the following.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.3.4
Once the Receive STS-3 TOH Processor block reaches this state, then it has already declared the “SEF
Defect Condition”. For the duration that the Receive STS-3 TOH Processor block is operating in the “SEF =
1, LOF = 0” state, the Receive STS-3 TOH Processor block will be testing the Framing Alignment bytes (A1
and A2) within the incoming STS-3 signal, in order to determine if it should declare the “LOF” or the “In-
Frame” condition.
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
RDI-L
B
B
RUR
5. It will set Bit 1 (SEF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0”
R/O
6. It will generate the “Change of SEF Defect Condition” interrupt. The XRT94L33 will indicate that it is
a. Toggling the “INT*” input pin “low” and
b. Setting Bit 1 (Change of SEF Defect Condition Interrupt Status), within the “Receive STS-3 Transport
IT
IT
0
0
7
7
to “1”, as depicted below.
generating this interrupt by doing the following.
Interrupt Status Register – Byte 0” as depicted below.
The In-Frame State
The SEF = 1, LOF = 0 State
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
S1 Byte
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
6
6
Detection of
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Status
B
B
Error
RUR
R/O
IT
IT
0
0
4
4
342
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Status
B
B
Error
RUR
R/O
IT
IT
0
0
3
3
LOF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
LOF
R/O
IT
IT
0
0
2
2
SEF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
SEF
R/O
IT
IT
1
1
1
1
xr
LOS Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
LOS
R/O
IT
IT
0
0
0
0