XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 443

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.3.5.1
The Receive UTOPIA output interface complies with UTOPIA Level 1, 2 and 3 standard interface (e.g., the
Receive UTOPIA can support both Single-PHY and Multi-PHY operations). Additionally, the XRT94L33
provides the user will the option of varying the following features associated with the Receive UTOPIA Bus
interface.
• Operating the Receive UTOPIA Data Bus per the UTOPIA Levels 1, 2 or 3 standards
• Receive UTOPIA Data Bus width of 8 or 16 bits.
• The cell size (e.g., the number of octets being processed per cell via the UTOPIA bus)
• Assigning a UTOPIA Address to a given STS-3c port.
• Whether the Receive UTOPIA Clock De-Skewing PLL is enabled or not.
Figure 112 presents a simple illustration of the Receive UTOPIA Interface block, along with its external input
pins.
Figure 112 A Simple Illustration of the Receive UTOPIA Interface block
A discussion of the operation of the Receive UTOPIA Bus Interface along with each of these options will be
presented below.
2.3.5.1.1
The ATM Layer processor will interface to the Receive UTOPIA Interface block via the following pins.
• RxUData[15:0] - Receive UTOPIA Data Bus output pins.
• RxUAddr[4:0] - Receive UTOPIA Address Bus input pins.
• RxUClk - Receive UTOPIA Interface Block clock input pin.
• RxUSoC - Receive “Start of Cell” Indicator output pin.
• RxUPrty - Receive UTOPIA - Odd Parity output pin.
• RxUEnB* - Receive UTOPIA Data Bus - Output Enable input pin.
• RxUClav/RxFullB* - RxFIFO Cell Available output pin.
Each of these signals is briefly discussed below.
RxUData[15:0] - Receive UTOPIA Data Bus outputs
The ATM Layer Processor will read ATM cell data from the Receive UTOPIA Interface block in a byte-wide (or
16-bit word-wide) manner, via these output pins. The Receive UTOPIA Data bus can be configured to
operate in the “8 bit wide” or “16 bit wide” mode (See Section _). If the “8-bit wide” mode is selected, then
only the RxUData[7:0] output pins will be active and capable of transmitting data to the ATM Layer Processor.
If the 16-bit wide mode is selected, then all 16 output pins (e.g., RxUData[15:0]) will be active. The Receive
UTOPIA Data bus is tri-stated while the active low RxUEnB* (Receive UTOPIA Bus - Output Enable) input
signal is “high”. Therefore, the ATM Layer Processor must assert this signal (e.g., toggle RxUEnB* low) in
order to read the ATM cell data from the Receive UTOPIA Interface block. The data on the Receive UTOPIA
Data Bus output pins are updated on the rising edge of the Receive UTOPIA Interface block clock signal,
RxUClk.
RxUAddr[4:0] - Receive UTOPIA Address Bus inputs
These input pins are used only when the XRT94L33 is operating in the Multi-PHY mode. Therefore, for more
information on the Receive UTOPIA Address Bus, please see Section _.
R
ECEIVE
The Pins of the Receive UTOPIA Bus Interface
UTOPIA B
US
O
UTPUT
I
NTERFACE
443
XRT94L33
Rev.1.2.0.