XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 142

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Once these events have occurred, then (as far as the XRT94L33 is concerned) the interrupt has been
serviced.
1.4.1.1
If the interrupt service routine is currently servicing an “Receive STS-3 TOH Processor” Block Interrupt, then
reading out the contents of the corresponding register (as presented in Table _) should result in the following
occurrences.
Once these events have occurred, then (as far as the XRT94L33 is concerned) the interrupt has been
serviced.
The remainder of the user’s interrupt service routine should now execute the appropriate steps to respond to
the conditions causing this interrupt request.
1.4.1.2
If the interrupt service routine is currently servicing interrupts associated with the following blocks.
• Receive ATM Cell Processor Block
• Receive PPP Packet Processor Block
• Receive STS-3c/SONET POH Processor Block
• Transmit ATM Cell Processor Block
• Transmit PPP Packet Processor Block
• DS3/E3 Mapper Block
• DS3/E3 Framer Block
Then there are still more steps that the µP/µC must take in order to fully service these interrupts.
STEP 3 – IDENTIFY THE INTERRUPTING CHANNEL
For each of the “above-mentioned” blocks, the user was advised (in Table 9) to read out the contents of a
“Channel Interrupt Indicator” Register. This register will uniquely identify the “interrupting” channel.
For example, the bit-format of the “Operation Channel Interrupt Indicator – Receive STS-3c/SONET POH
Processor Block” register is presented below.
4. The XRT94L33 will negate the “INT*” (Interrupt Request) output pin.
1. The µC/µP will uniquely identify the source or condition causing the interrupt request.
2. The “asserted interrupt status” bit-fields within these registers will be reset upon read.
3. The “asserted” bit-field(s), within the Operation Block Interrupt Status Register will be reset.
4. The XRT94L33 will negate the “INT*” (Interrupt Request) output pin.
I
I
NTERRUPT
NTERRUPT
S
S
ERVICING FOR THE
ERVICING FOR THE REMAINING BLOCKS WITHIN THE
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
“R
ECEIVE
STS-3 TOH P
142
ROCESSOR
XRT94L33
” B
LOCK
xr