XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 175

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
of ATM cell data, it is also sampling and latching the value of the corresponding parity bit (via the “TxUPrty”
input pin).
“TxFIFO” for further processing by the Transmit ATM Cell Processor block.
As the Transmit ATM Cell Processor block reads out the contents of the ATM cells (and corresponding parity
information) from the TxFIFO, it will route this data to the “Parity-Checker” block. The Parity Check block will
then compute the parity value of each byte or 16-bit word (of ATM cell data that is read from the TxFIFO).
Afterwards, the Parity Checker block will then compare the value of this “locally-computed” parity bit, with the
corresponding sampled parity value (originating from the “TxUPrty” input pin).
If the “locally-computed” and the “ATM Layer Processor” supplied parity values match then this byte (or 16-bit
word) of ATM cell data is deemed to be “error-free” and the parity-checker block will proceed to check and
verify the parity value of the very next byte (or 16-bit word) of ATM cell data. On the other hand, if there is a
discrepancy between the “locally-computed” the “ATM Layer Processor” supply parity values, then the “Parity-
Checker” block will declare a “Transmit UTOPIA Interface – Parity Error” event, and this entire ATM cell is
subject to being discarded (depending upon user configuration).
2.2.5.1
The Transmit ATM Cell Processor block provides the user with the following parity-checking features.
• To disable parity-checking altogether.
• To verify odd parity
• To verify even parity
• To retain cells that contain parity errors
• To discard cells that contain parity errors
Each of these “Transmit ATM Cell Processor” block parity options are discussed below.
2.2.5.2
The Transmit ATM Cell Processor block permits the user to either enable or disable the “Parity Verification” of
all bytes/words of ATM cells that have been read out of the TxFIFO. The user can accomplish this by writing
the appropriate data into Bit 5 (Parity Check Enable) within the Transmit ATM Control – Byte 0 Register; as
depicted below.
Transmit ATM Control – Byte 0 Register (Address = 0xNF03)
Setting this bit-field to “1” configures the Transmit ATM Cell Processor block to check and verify parity of all
incoming “user” cells. Conversely, setting this bit-field to “0” disables parity checking by the Transmit ATM
Cell Processor block.
2.2.5.3
The Transmit ATM Cell Processor block can be configured to check and verify either even or odd parity. The
user can implement this selection by writing the appropriate value into Bit 3 (Odd Parity) within the “Transmit
ATM Control – Byte 0” Register; as depicted below.
HEC Byte
Invert
B
R/W
IT
0
7
H
E
C
All sampled byte/words and their corresponding sampled parity value will be loaded into the
NABLING
OW THE
ONFIGURING THE
HEC Byte
Enable
Check
B
R/W
IT
0
6
T
/D
RANSMIT
ISABLING
Parity Check
T
Enable
RANSMIT
ATM C
B
R/W
IT
X
P
ARITY
5
ELL
ATM C
C
HECKING WITHIN THE
Discard Cell
P
upon Parity
ROCESSOR
B
Error
R/W
IT
0
ELL
4
P
ROCESSOR BLOCK TO CHECK
175
B
LOCK VERIFIES
Odd Parity
B
R/W
IT
0
T
3
RANSMIT
P
C
ARITY
B
ELL
R/O
IT
0
2
P
ROCESSOR
Unused
O
DD OR
B
R/O
E
IT
0
VEN
B
1
LOCK
P
ARITY
XRT94L33
Cell Payload
Scramble
Enable
Rev.1.2.0.
B
R/W
IT
0
0