XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 115

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
1.1.3
The purpose of the “Receive STS-3 TOH Processor” block is to perform the following functions.
• To receive an STS-3 signal from the remote terminal via optical fiber and a PECL interface, or via the
“Receive STS-3 Telecom Bus Interface.
• To declare and clear the LOS, SEF, LOF and AIS-L defect conditions.
• To declare and clear the RDI-L, SD and SF defect conditions.
• To optionally transmit the AIS-P indicator (downstream, towards the Receive STS-3c POH Processor block)
upon declaration of the AIS-L, LOS, LOF, SD or SF defect conditions.
• To compute and verify the B1 and B2 bytes of the incoming STS-3 signal.
• To detect and increment performance monitor registers anytime it detects any B1 and B2 byte errors.
• To receive and process Section Trace messages via the J0 byte.
• To terminate the Transport Overhead (TOH) within the incoming STS-3 signal.
• To detect and increment performance monitor registers anytime it detects any REI-L events.
• To receive and process messages via the J0 byte.
• To terminate the Transport Overhead (TOH) within the incoming STS-3 signal.
• To the resulting STS-3c SPE data-stream to the Receive STS-3c POH Processor block.
1.1.4
The purpose of the “Receive STS-3c POH Processor” block is to perform the following functions.
• To receive the STS-3c signal (originally extracted from the incoming STS-3 signal) to terminate the Path
Overhead (POH).
• To declare and clear LOP-P, AIS-P, UNEQ-P, PLM-P, TIM-P, and the RDI-P defect conditions.
• To optionally transmit the AIS-P indicator, in the down-stream direction (towards the Receive ATM Cell or
Receive PPP Packet Processor Blocks) anytime (and for the duration that) the Receive STS-3c POH
Processor declares the AIS-P, LOP-P, UNEQ-P, PLM-P or TIM-P defect conditions
• To declare and clear the LOP-C and AIS-C defect condition.
• To compute and verify the B3 byte of the incoming STS-3 SPE.
• To detect and increment Performance Monitor registers anytime it detects B3 byte errors in the incoming
STS-3c SPE data-stream.
• To detect and increment performance monitor registers anytime it detects any REI-P events.
• To receive and process Path Trace messages via the J1 byte.
• To route the STS-3c SPE data to the Receive ATM Cell Processor or Receive PPP Packet Processor
blocks for further processing.
T
T
HE
HE
R
R
ECEIVE
ECEIVE
STS-3 TOH P
STS-3
C
POH P
ROCESSOR
ROCESSOR
B
B
LOCK
LOCK
115
XRT94L33
Rev.1.2.0.