XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 419

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
requirements. Cells that are discarded will not be routed to the “Parity Calculation and Insertion” block. Cells
that are NOT discarded will proceed on through the remainder of the Receive ATM Cell Processor block
circuitry (and RxFIFO), for further processing.
Setting this bit-field to “1” configures the Receive User Cell Filter to discard all cells that comply with the “user-
cell” filter requirements.
Conversely, setting this bit-field to “0” configures the Receive User Cell Filter to NOT discard the cells that
comply with the “user-cell” filter requirements.
DEFINING THE USER CELL FILTER SENSE
The Sense of a given Receive User Cell Filter is defined by the state of Bit 0 (User Cell Filter Sense) within
the “Receive ATM Filter Control – Byte 0” Register; as described below.
BIT 0 - USER CELL FILTER SENSE
Receive ATM Filter # 0 , # 1, # 2, # 3 Control – Byte 0 (Address = 0xN743, 0xN753, 0xN763, 0xN773)
This bit-field controls the “Filter Mode”. If the user sets this bit-field to “1” then the “Receive User-Cell” Filter
will act, per the settings within Bits 2 (Copy Cell Enable) and 1 (Discard Cell Enable) on cells with header byte
patterns MATCHING the “user-cell” filtering criteria. Conversely, setting this bit-field to “0” configures the
“Receive User-Cell” Filter to act, per the settings within Bits 2 (Copy Cell Enable) and 1 (Discard Cell Enable)
on cells with header byte patterns NOT MATCHING the “user-cell” filtering criteria.
SPECIFYING THE RECEIVE USER CELL FILTERING CRITERIA
As described above, each of the four Receive User Cell Filters (within the Receive ATM Cell Processor block)
can be configured to perform a variety of actions (e.g., copy cells, discard cells, etc); based upon whether the
Header Byte Patterns of User Cells MATCH; or DO NOT MATCH a particular “User-Defined” Filter criteria.
The “User-Defined” Filter criteria (for each of the four Receive User Cell Filter blocks, within the Receive ATM
Cell Processor block) are ultimately defined by the values residing within a total of eight (8) registers. Four of
these registers are referred to as “User Cell Filter – Pattern” Registers; and the remaining four registers are
referred to as “User Cell Filter – Check” Registers. Each of these register types are defined below.
RECEIVE USER CELL FILTER – PATTERN REGISTERS
The four User Cell Filter – Pattern Registers permit the user to specify the Header Byte Pattern for the
Receive User Cell Filter. There are four User Cell Filter – Pattern Registers (one for each of the four (4)
header bytes, within an ATM cell). The bit-format of these “User Cell Filter – Pattern Registers” is presented
below.
Receive ATM Filter # 0, # 1, # 2, # 3 Pattern – Header Byte 1 (Address = 0xN744, 0xN754, 0xN764,
0xN774)
B
B
R/W
R/O
IT
IT
0
0
7
7
B
B
R/W
R/O
IT
IT
0
0
6
6
Unused
B
B
R/W
R/O
IT
IT
0
0
5
5
User Cell Filter Pattern – Header Byte 1[7:0]
B
B
R/W
R/O
IT
IT
0
0
4
4
419
Filter Enable
User Cell
B
B
R/W
R/W
IT
IT
1
0
3
3
Copy Cell
Enable
B
B
R/W
R/W
IT
IT
X
0
2
2
Discard Cell
Enable
B
B
R/W
R/W
IT
IT
X
0
1
1
XRT94L33
Filter Sense
User Cell
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
X
0
0
0