XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 409

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
If the HEC Byte Verification Block detects a Single-Bit Error within the Header bytes of an ATM Cell:
1. It will generate the “Detection of Correctable HEC Byte Error” Interrupt. The Receive ATM Cell Processor
block will indicate that it is declaring the “Detection of Correctable HEC Byte Error” Interrupt, by doing the
following.
Receive ATM Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0 (Address =
0xN70B)
2. It will increment the “Receive ATM Cell Processor Block – Receive ATM Cell with Correctable HEC Byte
Error Count” Registers. This is 32-bit RESET-upon-READ register that resides at Address Locations 0xN730
through 0xN733. The bit format of these registers is presented below.
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 3 (Address = 0xN730)
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 2 (Address = 0xN731)
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 1 (Address = 0xN732)
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 0 (Address = 0xN733)
Insertion
Interrupt
Receive
Status
B
RUR
B
B
B
RUR
RUR
RUR
Cell
a. Toggling the “INT*” output pin “low”.
b. Setting Bit 3 (Detection of Correctable HEC Byte Error Interrupt Status), within the “Receive ATM Cell
IT
0
IT
IT
IT
0
0
0
7
7
7
7
Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
Overflow
Interrupt
Receive
Status
B
FIFO
RUR
B
RUR
B
RUR
B
RUR
IT
0
IT
IT
IT
0
0
0
6
6
6
6
Received Cells with Correctable HEC Byte Error Count[31:24]
Received Cells with Correctable HEC Byte Error Count[23:16]
Received Cells with Correctable HEC Byte Error Count[15:8]
Extraction
Overflow
Interrupt
Receive
Memory
Status
B
RUR
Cell
B
RUR
B
RUR
B
RUR
IT
0
IT
IT
IT
0
0
0
5
5
5
5
Overflow
Insertion
Receive
Memory
Interrupt
Status
B
RUR
Cell
IT
B
RUR
B
RUR
B
RUR
0
IT
IT
IT
0
0
0
4
4
4
4
409
Detection of
Correctable
HEC Byte
Interrupt
Status
B
Error
RUR
IT
1
B
RUR
B
RUR
B
RUR
IT
IT
IT
3
0
0
0
3
3
3
Uncorrectable
Error Interrupt
Detection of
HEC Byte
Status
B
RUR
B
RUR
B
RUR
B
RUR
IT
0
IT
IT
IT
0
0
0
2
2
2
2
Clearance
Interrupt
of LCD
Defect
Status
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
0
0
0
IT
0
1
1
1
1
XRT94L33
Declaration
Interrupt
of LCD
Defect
Status
Rev.1.2.0.
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
IT
0
0
0
0
0
0
0
0