HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 92

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.15
The overflow prevention function (saturation operation) is specified by the S bit of the SR register.
This function is valid for arithmetic operations executed by the DSP unit and multiply and
accumulate operations executed by the existing SH-1 and SH-2. An overflow occurs when the
operation result exceeds the bounds that can be expressed as a two’s complement (not including
the guard bits).
Table 4.29 shows the overflow definitions for fixed decimal point arithmetic operations. Table
4.30 shows the overflow definitions for integer arithmetic operations. Multiply/Accumulate
calculation instructions (MAC) supported by previous SuperH RISC engines are performed on 64-
bit registers (MACH and MACL), so the overflow value differs from the maximum and minimum
values. They are defined exactly the same as before.
Table 4.29 Overflow Definitions for Fixed Decimal Point Arithmetic Operations
Sign
Positive
Negative
Table 4.30 Overflow Definitions for Integer Arithmetic Operations
Sign
Positive
Negative
Note:
When the overflow prevention function is specified, overflows do not occur. Naturally, the
overflow bit (V bit) is not set. When the CS bits specify overflow mode, the DC bit is not set
either.
Rev. 5.00 Jun 30, 2004 page 76 of 512
REJ09B0171-0500O
* Don’t care bits have no effect.
Overflow Prevention Function (Saturation Operation)
Overflow Condition
Result > 1–2
Result < –1
Overflow Condition
Result > 2
Result < –2
–15
–15
–31
– 1
Maximum/Minimum
1–2
–1
Maximum/Minimum
2
–2
–15
–15
–31
– 1
Hexadecimal Display
007FFFFFFF
FF80000000
Hexadecimal Display
007FFF****
FF8000****