HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 431

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Relationship Between Position of Instructions Located in On-Chip ROM/RAM or On-Chip
Memory and Contention Between IF and MA (SH-1 and SH-2): When an instruction is located
in on-chip memory (ROM/RAM) or on-chip cache, there are instruction fetch stages (‘if’ written
in lower case) that do not generate bus cycles as explained in section 7.4.2 above. When an if is in
contention with an MA, the slot will not split, as it does when an IF and an MA are in contention,
because ifs and MAs can be executed simultaneously. Such slots execute in the number of states
the MA requires for memory access, as illustrated in figure 7.8.
When programming, avoid contention of MA and IF whenever possible and pair MAs with ifs to
increase the instruction execution speed. Instructions that have 4 (5)-stage pipelines of IF, ID, EX,
MA, (WB) prevent stalls when they start from the longword boundaries in on-chip memory (the
(On-chip memory
or on-chip cache)
Instruc-
Instruc-
Instruc-
Instruc-
Instruc-
tion 1
tion 3
tion 5
tion 3
tion 5
Figure 7.7 Relationship Between IF and Location of Instructions in On-Chip Memory
32 bits
Instruc-
Instruc-
Instruc-
Instruc-
Instruc-
Instruc-
tion 2
tion 4
tion 6
tion 2
tion 4
tion 6
Fetching from an instruction (instruction 1) located on a longword boundary
Fetching from an instruction (instruction 2) located on a word boundary
... Instruction 1
... Instruction 3
... Instruction 5
... Instruction 2
... Instruction 3
... Instruction 5
Instruction 2
Instruction 4
Instruction 6
Instruction 4
Instruction 6
IF
IF
IF
ID
if
if
IF
if
: Bus cycle generated
: No bus cycle
: Bus cycle generated
: No bus cycle
EX
ID
ID
IF
IF
EX
EX
ID
ID
if
if
Rev. 5.00 Jun 30, 2004 page 415 of 512
EX
EX
ID
ID
IF
IF
EX
EX
ID
ID
if
if
Section 7 Pipeline Operation
EX
EX
ID
ID
EX
EX
REJ09B0171-0500O
: Slot
: Slot