HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 321

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2
Description: Adds the contents of the Sx and Sy operands and stores the result in the Dz operand.
When conditions are specified for DCT and DCF, the instruction is executed when those
conditions are TRUE. When they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Operation:
Format
PADD
Sx,Sy,Dz
DCT PADD
Sx,Sy,Dz
DCF PADD
Sx,Sy,Dz
/* PADD Sx,Sy,Dz */
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* ALU Sources assignment */
switch (xx) {
case 0x0: DSP_ALU_SRC1
case 0x1: DSP_ALU_SRC1
[if cc]PADD (Addition with Condition): DSP Arithmetic Operation Instruction
if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xff;
else
break;
if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xff;
else
Abstract
Sx+Sy Dz
if DC=1,Sx+Sy Dz
if 0,nop
if DC=0,Sx+Sy Dz
if 1,nop
/* Sx Operand selection bit (xx) */
DSP_ALU_SRC1G = 0x0;
DSP_ALU_SRC1G = 0x0;
Code
111110**********
10110001xxyyzzzz
111110**********
10110010xxyyzzzz
111110**********
10110011xxyyzzzz
= X0;
= X1;
Rev. 5.00 Jun 30, 2004 page 305 of 512
Cycle DC Bit
1
1
1
Section 6 Instruction Descriptions
Update
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SH-1 SH-2
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REJ09B0171-0500O
Instructions
Applicable
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—
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SH-
DSP