HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 229

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1.37
Description: Stores the effective address of the source operand into general register R0. The 8-bit
displacement is zero-extended and quadrupled. Consequently, the relative interval from the
operand is PC + 1020 bytes. The PC is the address four bytes after this instruction, but the lowest
two bits of the PC are corrected to B'00.
Note: If this instruction is placed immediately after a delayed branch instruction, the PC must
Operation:
Format
MOVA
MOVA(long d) /* MOVA @(disp,PC),R0 */
{
}
@(disp,PC),R0
long disp;
disp=(0x000000FF & (long)d);
R[0]=(PC&0xFFFFFFFC)+(disp<<2);
PC+=2;
point to an address specified by (the starting address of the branch destination) + 2.
MOVA (Move Effective Address): Data Transfer Instruction
Abstract
disp
4 + PC
R0
Code
11000111dddddddd
Rev. 5.00 Jun 30, 2004 page 213 of 512
Section 6 Instruction Descriptions
Cycle
1
T
Bit SH-1
—
REJ09B0171-0500O
Instructions
Applicable
SH-2
SH-
DSP