HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 514

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
7.4.7
Interrupt Exception Processing (Common): The interrupt is received during the ID stage of the
instruction and everything after the ID stage is replaced by the interrupt exception processing
sequence. The pipeline has ten stages: IF, ID, EX, EX, MA, MA, EX, MA, EX, and EX (figure
7.95). Interrupt exception processing is not a delayed branch. In interrupt exception processing, an
overrun fetch (IF) occurs. In branch destination instructions, the IF starts from the slot that has the
final EX in the interrupt exception processing.
Interrupt sources are external interrupt request pins such as NMI, user breaks, IRQ, and on-chip
peripheral module interrupts.
Address Error Exception Processing: The address error is received during the ID stage of the
instruction and everything after the ID stage is replaced by the address error exception processing
sequence. The pipeline has ten stages: IF, ID, EX, EX, MA, MA, EX, MA, EX, and EX (figure
7.96). Address error exception processing is not a delayed branch. In address error exception
processing, an overrun fetch (IF) occurs. In branch destination instructions, the IF starts from the
slot that has the final EX in the address error exception processing.
Address errors are caused by instruction fetches and by data reads or writes. See the Hardware
Manual for information on the causes of address errors.
Rev. 5.00 Jun 30, 2004 page 498 of 512
REJ09B0171-0500O
Branch destination
Branch destination
Next instruction
Next instruction
Exception Processing
Interrupt
Interrupt
Figure 7.96 Address Error Exception Processing Pipeline
......
......
Figure 7.95 Interrupt Exception Processing Pipeline
IF
IF
ID
ID
IF
IF
EX
EX
EX MA MA EX MA EX EX
EX MA MA EX MA EX EX
IF
IF
ID
ID
IF
IF
EX
EX
ID
ID
: Slot
: Slot