HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 45

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Addressing
Mode
Indirect
register
addressing
with displace-
ment
Indirect
indexed
register
addressing
Indirect
GBR
addressing
with
displace-
ment
Indirect
indexed
GBR
addressing
Instruction
Format
@(disp:4,
Rn)
@(R0, Rn)
@(disp:8,
GBR)
@(R0,
GBR)
Effective Addresses Calculation
The effective address is Rn plus a 4-bit displacement
(disp). The value of disp is zero-extended, and
remains the same for a byte operation, is doubled for
a word operation, or is quadrupled for a longword
operation.
The effective address is the Rn value plus R0.
The effective address is the GBR value plus an 8-bit
displacement (disp). The value of disp is zero-
extended, and remains the same for a byte
operation, is doubled for a word operation, or is
quadrupled for a longword operation.
The effective address is the GBR value plus R0.
(zero-extended)
(zero-extended)
GBR
1/2/4
Rn
R0
R0
GBR
1/2/4
disp
disp
Rn
+
+
+
+
Rev. 5.00 Jun 30, 2004 page 29 of 512
+ disp
GBR + R0
+ disp
Rn + R0
GBR
Rn
Section 4 Instruction Features
1/2/4
1/2/4
REJ09B0171-0500O
Formula
Byte: Rn +
disp
Word: Rn +
disp
Longword:
Rn + disp
Rn + R0
Byte: GBR +
disp
Word: GBR +
disp
Longword:
GBR + disp
4
GBR + R0
2
2
4