HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 10

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.8
4.9
4.10 Fixed Decimal Point Multiplication.................................................................................. 60
4.11 Shift Operations ................................................................................................................ 62
4.12 The MSB Detection Instruction ........................................................................................ 66
4.13 Rounding........................................................................................................................... 71
4.14 Condition Select Bits (CS) and the DSP Condition Bit (DC) ........................................... 74
4.15 Overflow Prevention Function (Saturation Operation) ..................................................... 76
4.16 Data Transfers................................................................................................................... 77
4.17 Operand Contention .......................................................................................................... 81
4.18 DSP Repeat (Loop) Control.............................................................................................. 83
4.19 Conditional Instructions and Data Transfers..................................................................... 91
Section 5 Instruction Set
5.1
Rev. 5.00 Jun 30, 2004 page viii of xiv
REJ09B0171-0500O
4.7.2
4.7.3
4.7.4
4.7.5
ALU Integer Operations.................................................................................................... 56
ALU Logical Operations................................................................................................... 58
4.9.1
4.9.2
4.9.3
4.9.4
4.11.1 Arithmetic Shift Operations ................................................................................. 63
4.11.2 Logical Shift Operations ...................................................................................... 64
4.12.1 Function ............................................................................................................... 66
4.12.2 Instructions and Operands.................................................................................... 70
4.12.3 DC Bit.................................................................................................................. 70
4.12.4 Condition Bits ...................................................................................................... 71
4.13.1 Operation Function .............................................................................................. 71
4.13.2 Instructions and Operands.................................................................................... 73
4.13.3 DC Bit.................................................................................................................. 73
4.13.4 Condition Bits ...................................................................................................... 74
4.13.5 Overflow Prevention Function (Saturation Operation) ........................................ 74
4.16.1 X and Y Memory Data Transfer .......................................................................... 77
4.16.2 Single Data Transfers........................................................................................... 78
4.18.1 Actual programming ............................................................................................ 86
Instruction Set for CPU Instructions ................................................................................. 93
5.1.1
5.1.2
5.1.3
Instructions and Operands.................................................................................... 52
DC Bit.................................................................................................................. 53
Condition Bits ...................................................................................................... 55
Overflow Prevention Function (Saturation Operation) ........................................ 56
Function ............................................................................................................... 58
Instructions and Operands.................................................................................... 59
DC Bit.................................................................................................................. 59
Condition Bits ...................................................................................................... 60
Data Transfer Instructions.................................................................................... 97
Arithmetic Instructions ........................................................................................ 99
Logic Operation Instructions ............................................................................... 102
.................................................................................................... 93