HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 192

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
Example:
Rev. 5.00 Jun 30, 2004 page 176 of 512
REJ09B0171-0500O
JSR_TABLE: .data.l
TRGET:
Note: When a delayed branch instruction is used, the branching operation takes place after the
slot instruction is executed, but the execution of instructions (register update, etc.) takes
place in the sequence delayed branch instruction
example, even if a delayed slot instruction is used to change the register where the
branch destination address is stored, the register content previous to the change will be
used as the branch destination address.
MOV.L
JSR
XOR
ADD
...........
.align
NOP
MOV
RTS
MOV
JSR_TABLE,R0
@R0
R1,R1
R0,R1
4
TRGET
R2,R3
#70,R1
; Address of R0 = TRGET
; Branches to TRGET
; Executes XOR before branching
;
procedure is completed (PR data)
; Jump table
;
;
; Returns to the above ADD instruction
; Executes MOV before RTS
Return address for when the subroutine
Procedure entrance
delayed slot instruction. For