HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 191

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1.26
Description: Branches to the subroutine procedure at the address specified by register indirect
addressing. The PC value is stored in the PR. The jump destination is an address specified by the
32-bit data in general register Rm. The stored/saved PC is the address four bytes after this
instruction. The JSR instruction and RTS instruction are used together for subroutine procedure
calls.
Note: Since this is a delayed branch instruction, the instruction after JSR is executed before
Operation:
Format
JSR
JSR(long m)
{
}
PR=PC;
PC=R[m]+4;
Delay_Slot(PR+2);
@Rm PC
branching. No interrupts and address errors are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
Instruction)
JSR (Jump to Subroutine): Branch Instruction (Class: Delayed Branch
Abstract
PR, Rm
/* JSR @Rm */
PC
Code
0100mmmm00001011 2
Rev. 5.00 Jun 30, 2004 page 175 of 512
Cycle T Bit SH-1 SH-2
Section 6 Instruction Descriptions
—
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP