HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 209

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1.32
Description: Does signed multiplication of 16-bit operands obtained using the contents of general
registers Rm and Rn as addresses. The 32-bit result is added to contents of the MAC register, and
the final result is stored in the MAC register. Rm and Rn data are incremented by 2 after the
operation.
When the S bit is cleared to 0, the operation is 16
the 64-bit result is stored in the coupled MACH and MACL registers.
When the S bit is set to 1, the operation is 16
addition to the MAC register is a saturation operation. For the saturation operation, only the
MACL register is enabled and the result is limited to a range of H'80000000 (minimum) and
H'7FFFFFFF (maximum).
If an overflow occurs, the LSB of the MACH register is set to 1. The result is stored in the MACL
register. The result is limited to a value between H'80000000 (minimum) for overflows in the
negative direction and H'7FFFFFFF (maximum) for overflows in the positive direction.
Note: When the S bit is 0, the SH-2 and SH-DSP CPU perform a 16
Format
MAC.W @Rm+,
MAC
@Rn+
@Rm+,
@Rn+
and accumulate operation and the SH-1 CPU performs a 16
and accumulate operation.
MAC.W (Multiply and Accumulate Calculation Word): Arithmetic Instruction
Abstract
With sign, (Rn)
+ MAC
MAC
(Rm)
Code
0100nnnnmmmm1111 3/(2)
16 + 32
16 + 64
Rev. 5.00 Jun 30, 2004 page 193 of 512
32-bit multiply and accumulate and
64-bit multiply and accumulate and
Section 6 Instruction Descriptions
Cycle
16 + 42
16 + 64
T
Bit SH-1 SH-2
—
—
REJ09B0171-0500O
42 bit multiply
Instructions
Applicable
64 bit multiply
SH-
DSP