HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 27

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The following instructions set addresses in the RS, RE registers for zero overhead repeat control:
The GBR and VBR registers are the same as the previous SuperH registers. Four control bits
(DMX, DMY, RF1, and RF0 bits) and an RC counter have been added to the SR register. The RS,
RE, and MOD registers are new registers.
2.3
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply
and accumulate registers store the results of multiply and multiply and accumulate operations. The
procedure register stores the return address from the subroutine procedure. The program counter
indicates the address of the program executing and controls the flow of the processing. The PC
counter points to four bytes ahead of the instruction currently executing. These registers are the
same as the SuperH microprocessor registers.
LDRS
LDRE
31
31
31
Note:
System Registers
@(disp, PC); disp
@(disp, PC); disp
These are used only when executing an instruction that was supported
by SH-1 and SH-2. They are not used for multiplication instructions newly
added for the SH-DSP (PMULS).
Figure 2.5 Organization of the System Registers
MACH
MACL
PR
PC
9
2 + PC
2 + PC
0
0
0
RS
RE
Multiply and accumulate register high
(MACH) Multiply and accumulate
register low (MACL)
These are the registers for storing the
results of multiply and accumulate
operations. On the SH-2 CPU, MACH
has 32 valid bits. On the SH-1 CPU, only
the lower 10 bits of MACH are valid, and
data is sign extended to 32 bits when read.
Procedure register (PR)
This register is used to store the return
destination addresses for subroutine
procedures.
Program counter (PC)
The PC indicates the next four bytes
(two instructions) following the instruction
currently being executed.
Rev. 5.00 Jun 30, 2004 page 11 of 512
Section 2 Register Configuration
REJ09B0171-0500O