HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 100

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
There are several restrictions on repeat control:
1. At least one instruction must come between the SETRC instruction and the first instruction of
2. Execute the SETRC instruction after executing the LDRS and LDRE instructions.
3. When there are more than four instructions for the repeat program (loop) and there is no repeat
4. When there are three or fewer instructions in the loop, branch instructions (BRA, BSR, BT,
Table 4.33 PC Values Pushed Out (1)
Conditions
RC>=2
RC=1
5. If there are four or fewer instructions in the loop, branched instructions (BRA, BSR, BT, BF,
Table 4.34 PC Values Pushed Out (2)
Conditions
RC>=2
RC=1
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REJ09B0171-0500O
RptEnd:
the repeat program (loop).
start address (in the above example, it was address instr1) at the long word boundary, one cycle
stall (cycle awaiting execution) is required for each repeat.
BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP), repeat control instructions (SETRC,
LDRS, LDRE), SR, RS, and RE load instructions, and TRAPA cannot be used. If they are
described, error exemption processing is started and the address values shown in table 4.33 are
pushed out to the stack area pointed by R15.
BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP), repeat control instructions (SETRC,
LDRS, LDRE), SR, RS, and RE load instructions, and TRAPA cannot be used for the last
three instructions in the repeat program (loop). If they are described, error exception
processing is started and the address values shown in table 4.34 are pushed out to the stack
area pointed by R15. In case of repeat control instruction (SETRC, LDRS, LDRE), and SR,
RS, and RE load instructions, they cannot be described in positions other than the repeat
module. If described, proper operation cannot be secured.
instr5;
instr6;
Position
Any
Any
Position
instr3
instr4
instr5
Any
Address Pushed Out
RptStart
Program address of illegal instruction
Address Pushed Out
Program address of illegal instruction
RptStart-4
RptStart-2
Program address of illegal instruction