HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 497

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Double-Length Multiplication Instructions (SH-2 CPU, SH-DSP): Include the following
instruction types:
The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm (figure 7.72). The
second MA accesses the multiplier. The mm indicates that the multiplier is operating. The mm
operates for four cycles after the MA ends, regardless of slot. The ID of the instruction following
the DMULS.L instruction is stalled for 1 slot (see the description of the Multiply/Accumulate
instruction). The two MA stages of the DMULS.L instruction, when they contend with IF, split the
slot as described in section 7.2.1, Contention between Instruction Fetch (IF) and Memory Access
(MA).
When an instruction that does not use the multiplier comes after the DMULS.L instruction, the
DMULS.L instruction may be considered to be a five-stage pipeline instruction of IF, ID, EX,
MA, and MA. In such cases, it operates like a normal pipeline. When an instruction that uses the
multiplier come after the DMULS.L instruction, however, contention occurs with the multiplier,
so operation is different from normal.
This occurs in the following cases:
1. When a MAC.L instruction is located immediately after a DMULS.L instruction
2. When a MAC.W instruction is located immediately after a DMULS.L instruction
3. When a DMULS.L instruction is located immediately after another DMULS.L instruction
4. When a MULS.W instruction is located immediately after a DMULS.L instruction
5. When an STS (register) instruction is located immediately after a DMULS.L instruction
6. When an STS.L (memory) instruction is located immediately after a DMULS.L instruction
7. When an LDS (register) instruction is located immediately after a DMULS.L instruction
8. When an LDS.L (memory) instruction is located immediately after a DMULS.L instruction
DMULS.L
DMULU.L
MUL.L
Third instruction
Next instruction
Instruction A
Rm, Rn
Rm, Rn
Rm, Rn
......
Figure 7.72 Multiplication Instruction Pipeline
IF
ID
IF
EX
—
MA
ID
IF
MA
EX
ID
Rev. 5.00 Jun 30, 2004 page 481 of 512
mm
MA
EX
mm
WB
MA
Section 7 Pipeline Operation
mm
WB
REJ09B0171-0500O
mm
: Slot