HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 131

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3
DSP operation instructions are digital signal processing instructions that are processed by the DSP
unit. Their instruction code is 32 bits long. Multiple instructions can be processed in parallel. The
instruction code is divided into two fields, A and B. Field A specifies a parallel data transfer
instruction and field B specifies a single or double data operation instruction. Instructions can be
specified independently, and their execution is independent and in parallel. Parallel data transfer
instructions specified in field A are exactly the same as double data transfer instructions.
The data operation instructions of field B are of three types: double data operation instructions,
conditional single data operation instructions, and unconditional single data operation instructions.
Table 5.15 shows the format of DSP operation instructions. The operands are selected
independently from the DSP register. Table 5.16 shows the correspondence of DSP operation
instruction operands and registers.
Table 5.15 Instruction Formats for DSP Operation Instructions
Classification
Double data operation instructions
(6 operands)
Conditional single
data operation
instructions
Unconditional single
data operation
instructions
DSP Operation Instruction Set
3 operands
2 operands
1 operand
3 operands
2 operands
Instruction Forms
ALUop. Sx, Sy, Du
MLTop. Se, Sf, Dg
ALUop. Sx, Sy, Dz
DCT ALUop. Sx, Sy, Dz
DCF ALUop. Sx, Sy, Dz
ALUop. Sx, Dz
DCT ALUop. Sx, Dz
DCF ALUop. Sx, Dz
ALUop. Sy, Dz
DCT ALUop. Sy, Dz
DCF ALUop. Sy, Dz
ALUop. Dz
DCT ALUop. Dz
DCF ALUop. Dz
ALUop. Sx, Sy, Du
MLTop. Se, Sf, Dg
ALUop. Sx, Dz
ALUop. Sy, Dz
Rev. 5.00 Jun 30, 2004 page 115 of 512
Section 5 Instruction Set
Instruction
PADD PMULS,
PSUB PMULS
PADD, PAND, POR,
PSHA, PSHL, PSUB,
PXOR
PCOPY, PDEC,
PDMSB, PINC,
PLDS, PSTS, PNEG
PCLR, PSHA #imm,
PSHL #imm
PADDC, PSUBC,
PMULS
PCMP, PABS, PRND
REJ09B0171-0500O