HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 26

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Register Configuration
Table 2.1
Bits
27–16
11
10
9
8
7–4
3–2
1
0
31–28,
15–12
Dedicated load and store instructions are used to access the RS, RE, and MOD registers. For
example, to access the RS register, do the following:
Rev. 5.00 Jun 30, 2004 page 10 of 512
REJ09B0171-0500O
LDC
LDC.L @Rm+, RS;
STC
STC.L RS, @-Rn;
Name
Repeat counter (RC)
Specification of modulo
addressing for Y pointer
(DMY)
Specification of modulo
addressing for X pointer
(DMX)
Bit M
Bit Q
Interrupt request mask
(IMASK)
Repeat flag (RF1, RF0)
Saturation operation bit
(S)
Bit T
Reserved
Rm,
RS, Rn;
SR Register Bits
RS; Rm
(Rm)
RS
Rn-4
Rn
Function
Specifies the number of iterations for repeat (loop) control (2
to 4095)
1: Modulo addressing mode becomes valid for the Y memory
address register Ay (R6, R7)
1: Modulo addressing mode becomes valid for the X memory
address register Ax (R4, R5)
Used by the DIV0S/U and DIV1 instructions
Indicate the level of interrupt request accepted (0-15)
Used to control zero-overhead repeating (loop)
00: 1 step repeat
01: 2 step repeat
11: 3 step repeat
10: Repeat of 4 or more steps
Used by MAC and DSP instructions
1: Specifies saturation operation (prevents overflows)
For MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT, and
DT instructions:
0: FALSE
1: TRUE
For ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L,
SHLR/L, ROTR/L and ROTCR/L instructions:
1: Indicates a carry, borrow, overflow or underflow
0: Always reads 0; Always write 0.
RS, Rm+4
Rn, RS
RS
(Rn)
Rm