HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 325

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.3
Description: Adds the contents of the Sx and Sy operands and stores the result in the Du operand.
The contents of the top word of the Se and Sf operands are multiplied as signed and the result
stored in the Dg operand. These two processes are executed simultaneously in parallel.
The DC bit of the DSR register is updated according to the results of the ALU operation and the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated
according to the results of the ALU operation.
Note: Since the PMULS is fixed decimal point multiplication, the operation result is different
Operation:
Format
PADD Sx,Sy,Du
PMULS Se,Sf,Dg
/* PADD Sx,Sy,Du PMULS Se,Sf,Dg
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* Multiplier Sources assignment */
switch (ee) {
}
from that of MULS even though the source data is the same.
PADD PMULS (Addition & Multiply Signed by Signed): DSP Arithmetic
Operation Instruction
case 0x0: DSP_M_SRC1 = X0_HW;
case 0x1: DSP_M_SRC1 = X1_HW;
case 0x2: DSP_M_SRC1 = Y0_HW;
case 0x3: DSP_M_SRC1 = A1_HW;
break;
break;
break;
break;
Sx + Sy Du
MSW of Se
of Sf Dg
Abstract
/* Se Operand selection bit (ee) */
MSW
111110**********
0111eeffxxyygguu
Code
*/
Rev. 5.00 Jun 30, 2004 page 309 of 512
1
Cycle
Section 6 Instruction Descriptions
DC Bit
Update
REJ09B0171-0500O
SH-1
—
Instructions
Applicable
SH-2
—
SH-
DSP