HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 439

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 7.1 shows the correspondence between types of contention and instructions.
Table 7.1
Contention
None
MA contends with IF
Causes DSP operation contention
MA contends with IF
Causes memory load contention
MA contends with IF
Causes multiplier contention
Types of Contention and Instructions
Cycles
1
2
3/1
2/1
3
4
8
1
1
2
3
4
1
1
1
3
1
1 (to 3)*
Stages
3
3
3
3
3
5
9
5
4
4
6
6
5
4
5
5
4
6
Rev. 5.00 Jun 30, 2004 page 423 of 512
Instructions
Inter-register transfer instructions
Inter-register operations (except
multiplier type instructions)
Inter-register logic operation instructions
Shift instructions
System control ALU instructions
Unconditional branch instructions
Conditional branch instructions
Delayed conditional branch instruction
SLEEP instruction
RTE instruction
TRAP instruction
DSP operation instructions MOVX.W
(load) and MOVY.W (load) instructions
Memory store instructions
STS.L instruction (PR)
STC.L instruction
Memory logic operations
TAS instruction
MOVS.W (load) and MOVS.L (load)
instructions
MOVX.W (store) and MOVY.W (store)
instructions
Memory load instructions
LDS.L instruction (PR)
LDC.L instruction
Register to MAC transfer instructions
(MACH/MACL)
Memory to MAC transfer instructions
(MACH/MACL)
MAC to memory transfer instructions
(MACH/MACL)
Multiplication instructions
Section 7 Pipeline Operation
REJ09B0171-0500O