HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 278

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
6.1.69
Format
TRAPA
Description: Starts the trap exception processing. The PC and SR values are stored on the stack,
and the program branches to an address specified by the vector. The vector is a memory address
obtained by zero-extending the 8-bit immediate data and then quadrupling it. The PC is the start
address of the next instruction. TRAPA and RTE are both used together for system calls.
Operation:
Rev. 5.00 Jun 30, 2004 page 262 of 512
REJ09B0171-0500O
TRAPA(long i) /* TRAPA #imm */
{
}
long imm;
imm=(0x000000FF & i);
R[15]-=4;
Write_Long(R[15],SR);
R[15]-=4;
Write_Long(R[15],PC–2);
PC=Read_Long(VBR+(imm<<2))+4;
#imm
TRAPA (Trap Always): System Control Instruction
Abstract
PC/SR
(imm
4 + VBR)
Stack area,
PC
Code
11000011iiiiiiii
Cycle
8
T
Bit SH-1
—
Instructions
Applicable
SH-2
SH-
DSP