HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 425

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This section describes the operation of the pipelines for each instruction. This information is
provided to allow calculation of the required number of CPU instruction execution states (system
clock cycles).
7.1
7.1.1
Pipelines are composed of the following five stages:
1. IF (Instruction fetch)
2. ID (Instruction decode)
3. EX (Instruction execution)
4. MA (Memory access)
5. WB/DSP (W/D) (Write back (CPU core) or DSP (DSP unit))
These stages flow with the execution of the instructions and thereby constitute a pipeline. At a
given instant, five instructions are being executed simultaneously. The basic pipeline flow is as
shown in figure 7.1. The period in which a single stage is operating is called a slot and is indicated
by two-way arrows (
All instructions have at least the 3 stages IF, ID and EX, but not all have stages MA and WB/DSP.
The way the pipeline flows also varies with the type of instruction. Some pipelines differ,
however, because of contention between IF and MA.
Fetches instruction from the memory where the program is stored.
Decodes the instruction fetched.
Does data operations and address calculations according to the results of decoding.
Accesses data in memory. Generated by instructions that involve memory access, with some
exceptions.
Write Back: Returns the results of the memory access (data) to a register. Generated by
instructions that involve memory loads, with some exceptions.
DSP: Does operations using the DSP unit’s ALU and MAC. Also, the results of memory
accesses (data) are returned to registers; not generated during writes to memory or no operation
(NOP).
Basic Configuration of Pipelines
The Five-Stage Pipeline
Section 7 Pipeline Operation
.
Rev. 5.00 Jun 30, 2004 page 409 of 512
Section 7 Pipeline Operation
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