HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 76

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.9.4
The condition bits are set as follows.
4.10
Multiplication in the DSP unit is between signed single-length operands. It is processed in one
cycle. When double-length multiplication is needed, use the SuperH RISC engine’s double-length
multiplication.
Basically, the operation result for multiplication is 32 bits. When a register that has guard bits is
specified as the destination operand, it is sign-extended.
In the DSP unit, multiplication is a fixed decimal point arithmetic operation, not an integer
operation. This means the top words of the constant and multiplicand are entered into the MAC
operator. In SuperH RISC engine multiplication, the bottom words of the two operands are entered
into the MAC operator. The operation result thus is different from the SuperH RISC engine. The
SuperH RISC engine operation result is matched to the LSB of the destination, while the fixed
decimal point multiplication operation result is matched to the MSB. The LSB of the operation
result in fixed decimal point multiplication is thus always 0.
Figure 4.13 shows a flowchart of fixed decimal point multiplication.
Rev. 5.00 Jun 30, 2004 page 60 of 512
REJ09B0171-0500O
The N bit is the value of bit 31 of the operation result.
The Z bit is 1 when the operation result is zero; otherwise, the Z bit is 0.
The V bit is always 0.
The GT bit is always 0.
Condition Bits
Fixed Decimal Point Multiplication