HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 78

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
The overflow prevention function is valid for DSP unit multiplication. Specify it by setting the S
bit of the SR register is set to 1. When an overflow or underflow occurs, the operation result value
is the maximum or minimum value respectively. In DSP unit fixed decimal point multiplication,
overflows only occur for H'8000
result is H'80000000, which means –1.0 rather than the correct answer of +1.0. When the S bit is
1, the overflow prevention function is engaged and the result is H'007FFFFFFF.
4.11
The amount of shift in shift operations is specified either through a register or using a direct
immediate value. Other source operands and destination operands are registers. There are two
types of shift operations: arithmetic and logical. Table 4.21 shows the operation types. The
correspondence between operands and registers is the same as for ALU fixed decimal point
operations, except for immediate operands. The correspondence is shown in table 4.22.
Table 4.21 Types of Shift Operations
Mnemonic
PSHA Sx, Sy, Dz
PSHL Sx, Sy, Dz
PSHA #imm, Dz
PSHL #imm, Dz
–32
Table 4.22 Correspondence between Operands and Registers for Shift Operations
Operand
Sx
Sy
Dz
Note: Yes: Register can be used with operand.
Rev. 5.00 Jun 30, 2004 page 62 of 512
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imm1
Shift Operations
X0
Yes
Yes
+32, –16
Function
Arithmetic shift
Logical shift
Arithmetic shift with
immediate data
Logical shift with immediate
data
X1
Yes
Yes
imm2
+16
H'8000 ((–1.0)
Y0
Yes
Yes
Y1
Yes
Yes
Source 1
Sx
Sx
Dz
Dz
(–1.0)). When the S bit is 0, the operation
M0
Yes
Yes
Source 2
Sy
Sy
imm1
imm1
M1
Yes
Yes
A0
Yes
Yes
Destination
Dz
Dz
Dz
Dz
A1
Yes
Yes