HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 102

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.18.1
The repeat start register (RS) and repeat end register (RE) store the repeat start address and repeat
end address respectively. Addresses stored in these registers are changed depending on the number
of instructions in the repeat program (loop). This rule is shown below.
Repeat_Start:
Repeat_Start0: Address of instruction one higher than the repeat end instruction
Repeat_Start3: Address of instruction three higher than the repeat end instruction
Rev. 5.00 Jun 30, 2004 page 86 of 512
REJ09B0171-0500O
When RC=0: All interruptions and bus errors are accepted.
1-step repeat
Start(End):
When RC>=1
More than 4 steps repeat
Start:
End:
A: All interruption and bus error exceptions are accepted.
B: Only the bus error exception is accepted.
C: No interruption and bus error exceptions are accepted.
Actual programming
Figure 4.23 Restriction on Acceptance of Interruption by Repeat Module
instr0
instr1
instr n-3
instr n-2
instr n-1
instr n
instr n+1
:
:
Address of repeat start instruction
instr0
instr1
instr2
A
A or C (when returning from instr n)
A
A
B
C
C
C
A
:
A
B
C
A
2-step repeat
Start:
End:
instr0
instr1
instr2
instr3
A
B
C
C
A
Start:
End:
3-step repeat
instr0
instr1
instr2
instr3
instr4
A
B
C
C
C
A