HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 42

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
Table 4.2
SH-1/SH-2/SH-DSP CPU
BRA
ADD
Multiplication/Accumulation Operation:
SH-1 CPU: 16bit
16bit 16bit + 42bit
cycles.
SH-2/SH-DSP CPU: 16bit
cycles. 16bit
to three cycles. 32bit
multiplication/accumulation operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch (table 4.3). The number
of instructions after T bit in the status register is kept to a minimum to improve the processing
speed.
Table 4.3
SH-1/SH-2/SH-DSP CPU
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Immediate Data: Byte immediate data is located in instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. The memory
table is accessed by an immediate data transfer instruction (MOV) using the PC relative
addressing mode with displacement (table 4.4).
Rev. 5.00 Jun 30, 2004 page 26 of 512
REJ09B0171-0500O
TRGET
R1,R0
R1,R0
TRGET0
TRGET1
#–1,R0
#0,R0
TRGET
Delayed Branch Instructions
T Bit
16bit + 64bit
16bit
32bit
42-bit multiplication/accumulation operations are executed in two to three
32-bit multiplication operations are executed in one to three cycles.
16bit
Description
T bit is set when R0
program branches to TRGET0.
When R0
When R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0.
The program branches if R0 =
0.
64-bit multiplication/accumulation operations are executed in two
64-bit multiplication and 32bit
Description
Executes an ADD before
branching to TRGET.
32-bit multiplication operations are executed in one to two
R1 and to TRGET1.
R1. The
Example for Other CPU
ADD.W
BRA
Example for Other CPU
CMP.W
BGE
BLT
SUB.W
BEQ
32bit + 64bit
R1,R0
TRGET
R1,R0
TRGET0
TRGET1
#1,R0
TRGET
64-bit