HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 22

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Register Configuration
With DSP type instructions, eight of the 16 general registers are used in addressing the X and Y
data memory and the data memory that uses the I bus (single data).
To access X memory, R4 and R5 are used as the X address register [Ax] and R8 is used as the X
index register [Ix]. To access the Y memory, R6 and R7 are used as the Y address register [Ay]
and R9 is used as the Y index register [Iy]. To access single data using the I bus, R2, R3, R4, and
R5 are used as the single data address register and R8 as the single data index register [Is].
DSP type instructions can simultaneously access X and Y memory. There are two groups of
address pointers for specifying the X and Y data memory addresses.
Figure 2.2 shows the general registers.
Rev. 5.00 Jun 30, 2004 page 6 of 512
REJ09B0171-0500O
Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and
2. R15 functions as a hardware stack pointer (SP) during exception processing.
indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed
source register or destination register.
Figure 2.1 General Registers (SH-1 and SH-2)
31
R15, SP
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
*
1
(hardware stack pointer)
*
2
0