HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 512

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
MAC
instruction types:
The pipeline has four stages: IF, ID, EX, and MA (figure 7.91). MA is a stage for accessing the
memory and multiplier. MA contends with IF. This makes it the same as ordinary store
instructions. Since the multiplier does contend with the MA, however, the items noted for the
multiplication, Multiply/Accumulate, double-length multiplication, and double-length
multiply/accumulate instructions apply.
RTE Instruction (Common): RTE
The pipeline has five stages: IF, ID, EX, MA, and MA (figure 7.92). The MAs do not contend
with IF. RTE is a delayed branch instruction. The ID of the delay slot instruction is stalled 3 slots.
The IF of the branch destination instruction starts from the slot following the MA of the RTE.
Rev. 5.00 Jun 30, 2004 page 496 of 512
REJ09B0171-0500O
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
Memory Transfer Instructions (Common, or SH-DSP): Include the following
Branch destination
MACH, @–Rn
MACL, @–Rn
DSR,@–Rn (SH-DSP)
A0,@–Rn (SH-DSP)
X0,@–Rn (SH-DSP)
X1,@–Rn (SH-DSP)
Y0,@–Rn (SH-DSP)
Y1,@–Rn (SH-DSP)
Third instruction in series
Figure 7.91 MAC
Delay slot
RTE
Next instruction
.....
Instruction A
Figure 7.92 RTE Instruction Pipeline
IF
.....
ID
IF
Memory Transfer Instruction Pipeline
EX
—
IF
MA
—
ID
IF
MA
EX
ID
—
IF
MA
EX
ID
ID
IF
.....
EX
EX
ID
.....
.....
EX
: Slot
.....
: Slot