HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 513

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
TRAP Instruction (Common): TRAPA
#imm
: Slot
Instruction A
IF
ID
EX
EX MA
MA MA EX EX
Next instruction
IF
Third instruction in series
IF
EX .....
Branch destination
IF
ID
......
IF
ID
EX
Figure 7.93 TRAP Instruction Pipeline
The pipeline has nine stages: IF, ID, EX, EX, MA, MA, MA, EX, and EX (figure 7.93). The MAs
do not contend with IF. TRAP is not a delayed branch instruction. The two instructions after the
TRAP instruction are fetched, but they are discarded without being executed. The IF of the branch
destination instruction starts from the slot of the EX in the ninth stage of the TRAP instruction.
SLEEP Instruction (Common): SLEEP
: Slot
SLEEP
IF
ID
EX
Next instruction
IF
.....
Figure 7.94 SLEEP Instruction Pipeline
The pipeline has three stages: IF, ID and EX (figure 7.94). It is issued until the IF of the next
instruction. After the SLEEP instruction is executed, the CPU enters sleep mode or standby mode.
Rev. 5.00 Jun 30, 2004 page 497 of 512
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