HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 288

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
6.2.2
Single data transfers are instructions that load to and store from the DSP register. They are like
system register load and store instructions. Data transfers between the DSP register and memory
use the main buses. Like CPU core instructions, data accesses can create access contention with
instruction memory accesses.
Single data transfers can use either word or longword data. Figure 6.16 shows the load and store
operations in single data transfers.
Rev. 5.00 Jun 30, 2004 page 272 of 512
REJ09B0171-0500O
}
else { X_MEM=0; XAB=Unknown; }
IAB, IDB: Main buses
else {XDB=Dx[31:16];X R/W=0;}
IDB
IAB
Single Data Transfers (MOVS.W and MOVS.L)
32 bits
32 bits
Figure 6.16 Load and Store Operations in Single Data Transfers
31
Memory
R2 [As]
R3 [As]
R4 [As]
R5 [As]
31
MAB
0
0
Control is
SH core
/* Dx is A0 or A1 */
Instruction code for single
data transfer operation
Control
WL LS
DSP data register
input/output control