HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 426

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
7.1.2
The time period in which a single stage operates called a slot. Slots must follow the rules
described below.
All stages (IF, ID, EX, MA, WB/DSP) of an instruction must be executed in 1 slot. Two or more
stages cannot be executed within 1 slot. Since WB/DSP is executed immediately after MA,
however, some instructions may execute MA and WB/DSP within the same slot. Figures 7.2 and
7.3 show impossible pipeline flows.
Instruction Execution: Each stage (IF, ID, EX, MA, WB/DSP) of an instruction must be
executed in one slot. Two or more stages cannot be executed within one slot (figure 7.2), with
exception of WB and MA. Since WB is executed immediately after MA, however, some
instructions may execute MA and WB within the same slot.
Slot Sharing: A maximum of one stage from another instruction may be set per slot, and that
stage must be different from the stage of the first instruction. Identical stages from two different
instructions may never be executed within the same slot (figure 7.3).
Rev. 5.00 Jun 30, 2004 page 410 of 512
REJ09B0171-0500O
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Note: ID and EX of instruction 1 are executed in the same slot.
Slot and Pipeline Flow
Instruction 1
Instruction 2
IF
Time
ID
IF
Figure 7.1 Basic Structure of Pipeline Flow
IF
Figure 7.2 Impossible Pipeline Flow 1
EX
ID
IF
ID
IF
MA
EX
ID
IF
EX
WB/DSP
MA
EX
ID
IF
ID
WB/DSP
MA
EX
EX
ID
WB/DSP
MA W/D
MA
EX
WB/DSP
MA WB/DSP
: Slot
Instruction
stream
: Slot